1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit comprising logic circuitry which is operated in such a current mode to switch a current path thereof according to an applied signal.
2. Description of the Related Art
In general, semiconductor integrated circuits include logic circuits which executes desired logic operations on applied input signals. Such semiconductor integrated circuits are generally classified into a bipolar integrated circuit, a MOS (insulated gate) integrated circuit, and a BiCMOS integrated circuit (integrated circuit fabricated by combining bipolar transistors, p-channel MOS transistors and n-channel MOS transistors together) according to the type of transistors used as components.
The semiconductor integrated circuits are also grouped into a TTL logic circuit, an ECL logic circuit and a MOS logic circuit according to the potential or voltage levels for providing two possible status, "0" and "1" as the logic level. The TTL logic circuit is a circuit operating in a TTL level, which input "L" level is of the order of 0.8 V and which input "H" level is of the order of 2.0 V. In the ECL logic circuit, the input level of "L" is -1.7 V and the input level of "H" is -0.9 V. The MOS logic circuit is a circuit operating in a MOS level, whose input "L" level is of the order of 2.0 V and whose input "H" level is of the order of 4.0 V. The semiconductor integrated circuit including a logic circuit operating in an ECL level will be discussed in the below description. However, if a semiconductor integrated circuit includes, at an input stage thereof, a current switching circuit in which a current path is switched according to an input signal, any type of semiconductor integrated circuits may be referred to.
FIG. 1 is a diagram showing one example of the layout of a conventional semiconductor integrated circuit operated by a signal of an ECL level, which is fabricated on a chip. As one example of the semiconductor integrated circuit, an ECL RAM including a random-access memory as an internal function circuit is shown in FIG. 1.
Referring to FIG. 1, a memory cell array 1 for storing information is arranged in the center of a RAM chip 100. The memory cell array 1, although not shown, is provided with a plurality of memory cells arranged in the form of a matrix of rows and columns. An input/output signal of the RAM chip 100 is at an ECL level.
There are provided a plurality of input signal pads 9 for receiving input signals of ECL levels and input buffer circuits 10 provided in association with the input signal pads 9 along the outer periphery of the RAM chip 100. One of the input buffer circuits 10 receives a signal fed from an associated input signal pad 9 to perform a buffer processing on the signal, thereby generating an internal input signal. A specific arrangement of the input buffer circuit 10 will be described later. In the following description, a logic circuit receiving an externally applied signal or supplying a signal externally is particularly referred to as an input or output buffer circuit. That is, a buffer circuit is one of logic circuits.
In order to supply operating supply voltage to the ECL.multidot.RAM, the RAM chip 100 is also provided with a first power supply pad (hereinafter called merely "VCC pad") 2 to be supplied with a first supply voltage VCC, and a second power supply pad (hereinafter called merely "VEE pad") 3 to be supplied with a second supply voltage VEE&gt;.
Internal VCC power supply interconnections 4 are provided along the outer periphery of the RAM chip 100. The internal VCC power supply interconnections 4 connect the VCC pad 2 to each of the input buffer circuits 10, and supply the first supply voltage VCC applied to the VCC pad 2 to each of the input buffer circuits 10.
A reference potential generating circuit 11 for generating a reference potential VBB1 of a predetermined voltage level is provided near the VCC pad 2. The reference potential VBB1 generated by the reference potential generating circuit 11 is supplied to each of the input buffer circuits 10 through a reference potential VBB1 interconnection (hereinafter called merely "VBB interconnection") 8.
Internal VEE interconnections 12, which extend from the VEE pad 3, are connected to the respective input buffer circuits 10 in order to supply the second supply voltage VEE thereto. However, FIG. 1 shows only parts of the internal VEE interconnections 12 for simplification of the drawing figure.
The RAM chip 100 includes an address decoder used to select a particular address in the memory cell array 1 in response to a signal from one of the input buffer circuits 10, a data write circuit for writing data into the memory cell array 1, a data read circuit for reading out data therefrom, and peripheral circuits such as a circuit for outputting data from the data read circuit to an outside of the RAM chip 100, etc. However, they are also omitted for simplification of the drawing figure.
The reference potential VBB1 generated by the reference potential generating circuit 11 is used as an input logic threshold value in the input buffer circuits 10. An input signal applied to an input buffer circuit 10 through an associated input signal pads 9 is subjected to buffer processing when the reference potential VBB1 is used as the logic threshold value.
In the semiconductor integrated circuit which deals with the signal of the ECL level, the first supply voltage VCC supplied to the VCC pad 2 is ground potential (0 V), and the second supply voltage VEE supplied to the VEE pad 3 is -4.5 V or -5.2 V.
FIG. 2 is a diagram showing one example of the arrangement of the reference potential generating circuit 11. Referring to FIG. 2, the reference potential generating circuit 11 includes a first reference potential generating circuit hereinafter called merely "VBB0 generating circuit") 5 for generating a first reference potential VBB0 from the power supply voltage VCC fed through the internal VCC interconnection 4, and a second reference potential generating circuit (hereinafter called merely "VBB1 generating circuit") 6 for generating a second reference potential VBB1 in response to the first reference potential VBB0 from the VBB0 generating circuit 5.
The VBB0 generating circuit 5 comprises a resistor 201 having one end connected to the internal VCC interconnection 4 and the other end connected to an internal output node N10 as well as to a constant current source 301 provided between the output node N10 and the internal VEE interconnection 12.
The VBB1 generating circuit 6 includes an npn bipolar transistor 102 for level-shifting the first reference potential VBB0 from the VBB0 generating circuit 5 and a constant current source 303 for supplying constant current to the bipolar transistor 102. The bipolar transistor 102 has a base connected to the output node N10 of the VBB0 generating circuit 5, a collector connected to the internal VCC interconnection 4, and an emitter connected to the constant current source 303 and to an interconnection 8.
The constant current source 303 is provided between the emitter of the bipolar transistor 102 and the internal VEE interconnection 12. The operation of the reference potential generating circuit 11 will now be described below.
In the ECL circuit, the bipolar transistor 102 is operated in an unsaturated region for carrying out a processing operation at high speed. A description will be made later of the construction of each of the constant current sources 301 and 302. The constant current sources 301 and 303 are so constructed that they supply constant current at all times even when the second supply voltage VEE varies. The VBB0 generating circuit 5 outputs the first reference potential VBB0 from the node N10 at one end of the resistor 201. Assuming now that the current supplied in a direction indicated by the arrow in the figure from the constant current source 301 is I301, the resistance value of the resistor 201 is R201 and the voltage at the internal VCC interconnection 4 is V (4), the voltage at the node N10, i.e., the first reference potential VBB0 is given by the following equation: EQU VBB0=V (4)-I301.multidot.R201
Let's also assume that a voltage drop at the internal VCC interconnection 4 between the VCC pad 2 and the reference potential generating circuit 11 is .DELTA.V4. In this case, the voltage at the internal VCC interconnection 4 is given by the following equation: EQU V (4)=VCC-.DELTA.V4
Since VCC=0, the first reference potential VBB0 is represented by the following equation: EQU VBB0=-I301.multidot.R210-.DELTA.V4 (1)
The constant current source 303 supplies constant emitter current to the bipolar transistor 102. The bipolar transistor 102 is operated in an emitter follower to reduce the base voltage thereof by the emitter-base voltage VBE (0.8 V or so) to output the same. Thus, the voltage at the emitter of the bipolar transistor 102, i.e., the second reference potential VBB1 is given by the following equation: ##EQU1## The second reference potential VBB1 is used as the voltage for determining the logic threshold value of the input buffer circuit 10.
FIG. 3 is a diagram showing one example of the arrangement of one of the input buffer circuits 10. In FIG. 3, the input buffer circuit 10 includes an npn bipolar transistor 103 for level-shifting the input signal applied to the input signal pad 9, npn bipolar transistors 104, 105 for switching a current path according to the magnitudes of both the voltage at the emitter of the bipolar transistor 103 and the second reference potential VBB1, a constant current source 305 for supplying constant current to the bipolar transistor 104 and 105, and resistors 203, 204 for converting a current signal produced by the bipolar transistor 104 or 105 into a voltage signal, respectively.
The bipolar transistor 103 has a collector connected to the internal VCC interconnection 4, an emitter connected to the base of the bipolar transistor 104 and a constant current source 304, and a base connected to the input signal pad 9.
The bipolar transistors 104, 105 have emitters connected in common to the constant current source 305. The collector of the bipolar transistor 104 is electrically connected to the internal VCC interconnection 4 through the resistor 203. The collector of the bipolar transistor 105 is also electrically connected to the internal VCC interconnection 4 through the resistor 204. In addition, the base of the bipolar transistor 105 is electrically connected to the internal VBB1 interconnection 8. Internal input signals NA and A are outputted from the collectors of the bipolar transistors 104, 105, respectively.
The internal input signals A and NA are supplied, according to their kinds to an address selecting circuit, a write circuit or a read circuit, which are peripheral circuits of the memory cell array 1.
Each of the constant current sources 304, 305 has the other end connected to the internal VEE interconnection 12 through which current is supplied. The operation of the input buffer circuit 10 will now be described below.
Let's now consider a case where a signal VIH of a high level is supplied to the input signal pad 9. In this case, the signal VIH of the high level is shifted in level by the base-emitter voltage VBE of the bipolar transistor 103, and thereafter supplied to the base of the bipolar transistor 104. In the ECL circuit, all current substantially flows only in a bipolar transistor receiving a greatest base voltage, out of bipolar transistors whose emitters are connected in common. The remaining bipolar transistors therein supply little current. Such two states are referred to as "ON" and "OFF" states, respectively, in the below description.
The voltage at the base of the bipolar transistor 104 is VIH-VBE, while the voltage at the base of the bipolar transistor 105 is V (8). Here, the base voltage V (8) is equal to VBB1-.DELTA.V8 [i.e., V (8)=VBB1-.DELTA.V8], and .DELTA.V8 represents the amount of a voltage drop along the interconnection 8. If the base voltage of the bipolar transistor 104 is higher than that of the bipolar transistor 105, the transistor 104 is brought into the "ON" state. As a consequence, the current flows in a current path of the resistor 203, the bipolar transistor 104 and the constant current source 305, while no current flows through the resistor 204. Therefore, the voltage at the collector of the bipolar transistor 104 is rendered low in level, and the voltage at the collector of the bipolar transistor 105 is rendered high in level, whereby complementary internal signals NA and A are produced.
When the voltage of the signal inputted to the input signal pad 9 is in a low level VIL, the base voltage of the bipolar transistor 104 is brought into VIL-VBE. If (VIL-VBE) is smaller than V (8), the transistor 104 is brought into the "OFF" state, and the transistor 105 is brought into the "ON" state. As a consequence, the collector voltage of the bipolar transistor 104 is rendered high in level and the collector voltage of the bipolar transistor 105 is rendered low in level. Accordingly, the internal signal NA is brought into a high level and the internal signal A is brought into a low level.
The level of each of the internal input signals A, NA is determined by the level of the signal applied to the input signal pad 9 and the base voltage V (8) of the bipolar transistor 105. This means that the base voltage V (8) of the bipolar transistor 105 determines the logic threshold value of the input buffer circuit 10. If the base voltage V (8) of the bipolar transistor 105 meets the relation represented by the following inequality (3): EQU VIL-VBE&lt;V (8)&lt;VIH-VBE (3)
the input buffer circuit 10 is normally operated so as to generate the internal input signals A, NA corresponding to the level of the input signal.
Even when the base voltage V (8) of the bipolar transistor 105 meets the above inequality (3), in the following relation: EQU V (8)-(VIL-VBE).noteq.-V (8)+(VIH-VBE)
the switching speed of the input buffer circuit 10 differs from a case where the input signal is the high level VIH to a case where it is the low level VIL. Since the switching speed of the input buffer circuit 10 is determined by a slowest switching speed therein, its switching speed becomes slow, thereby deteriorating a high-speed response characteristic of the input buffer circuit 10. Since the operation margin of the input buffer circuit 10 is also determined by a smallest difference between the base voltage V (8) and the level of an input signal, its operation margin is also made small. Assuming that the voltage drop at the interconnection 8 is .DELTA.V8, the base voltage V (8) of the bipolar transistor 105 is obtained from the equation (2) as follows: EQU V (8)=VBB1-.DELTA.V4-.DELTA.V8 (4)
From the standpoint of the high-speed response characteristic and the operation margin, the ideal state is a state that the base voltage V (8) of the bipolar transistor 105 is set to an intermediate level between the high and low levels of the base voltage of the bipolar transistor 104, i.e., to the level of the voltage represented by the following expression: EQU {(VIH-VIL)/2}-VBE (5)
The arrangement and operation of each of the constant-current sources 301, 303, 304, 305 will now be described. Any one of circuits shown in FIGS. 4A through 4C may be used as the constant current source.
The constant current source shown in FIG. 4A is comprised of an npn bipolar transistor 401 and a resistor 410. The bipolar transistor 401 has a collector connected to a current supply node 20, a base connected to a constant bias voltage VCS, and an emitter connected to one end of the resistor 410. The other end of the resistor 410 is connected to the internal VEE interconnection 12. The current supply node 20 is connected to the resistors or the emitters of the bipolar transistors shown in FIGS. 2 and 3. Assuming that the current supplied to the current supply node 20 is I, the current I is given by the following equation: ##EQU2## where .DELTA.V12 represents the amount of a voltage drop over the internal VEE interconnection 12, "a" shows a positive proportion constant and R410 denotes the resistance value of the resistor 410. In the equation (6), the constant bias voltage VCS is generated so as to cancel the variation in the second internal supply voltage VEE (where VDIF is kept constant), and the current produced by this constant current source is kept constant at all times if the voltage drop .DELTA.V12 over the internal VEE interconnection 12 is neglected.
The constant current source shown in FIG. 4B includes an n-channel MOS transistor 402. The MOS transistor 402 has a gate supplied with a constant bias voltage VCS, one conduction terminal connected to the current supply node 20, and the other conduction terminal connected to the internal VEE interconnection 12. When the MOS transistor 402 is operated in a triode region, the drain current of the MOS transistor 402 is proportional to the square of the difference in voltage between the gate and source thereof. Therefore, the current I supplied to the current supply node 20 from the constant current source shown in FIG. 4B is given by the following equation: EQU I=K.multidot.(VDIF-.DELTA.V12).sup.2
The constant current source shown in FIG. 4C is a current-mirror type constant current circuit, which includes npn bipolar transistor 403, 404. The bipolar transistor 403 has a collector connected to a bias voltage VCS supply node through a resistor 411, a base connected to the collector thereof and to the base of the npn bipolar transistor 404, and an emitter connected to the internal VEE interconnection 12. The bipolar transistor 404 has a collector connected to the current supply node 20, a base to the base and collector of the npn bipolar transistor 403, and an emitter connected to the internal VEE interconnection 12. This constant current source supplies the same current amount as that which flows through the resistor 411 to the current source node 20. The current I thus supplied is given by the following equation: ##EQU3##
The arrangement and operation of a circuit for generating the constant voltage VCS will next be described below.
FIG. 5 is a diagram showing one example of the arrangement of the circuit for generating the constant voltage VCS. Referring to FIG. 5, the VCS generating circuit includes npn bipolar transistors Q1, Q2, Q3, Q4 and Q5, and resistors R1, R2, R3, R4 and R5.
The resistor R1 is connected between the internal VCC interconnection 4 and an internal node N12. The npn bipolar transistor Q1 has a collector connected to the internal node N12, a base connected to an internal node N14, and an emitter connected to the internal VEE interconnection 12. The bipolar transistor Q2 has a base connected to the internal VCC interconnection 4, and an emitter connected to one end of the resistor R2. The bipolar transistor Q3 has a collector connected to the other end of the resistor R2 through the internal node N14 and to the base of the npn bipolar transistor Q1, a base connected to an internal node N15, and an emitter connected to the internal VEE interconnection 12 through the resistor R3.
The npn bipolar transistor Q4 has a collector thereof connected to the internal VCC interconnection 4, a base connected to the internal node N12, and an emitter connected to a VCS output node VCS. Here, the output node and the voltage supplied thereto are denoted by like reference numerals. The npn bipolar transistor Q5 has a collector and a base connected together to the internal node N15 and an emitter connected to VEE interconnection 12. The resistor R4 is connected between the internal output node VCS and the internal node N15. A description will now be made of the operation of the VCS generating circuit.
The VCS generating circuit is constructed such that the difference between the second supply voltage VEE and the constant voltage VCS, i.e., VCS-VEE is kept constant at all times regardless of the variations in the constant voltage VCC and the second supply voltage VEE. Let's now assume that VDIF'=VCS-VEE. A description will be made below of that VDIF' is kept constant independent of the variations in the supply voltages VCC and VEE, using the equations to be described below. Let's now assume that the base-emitter voltages of the npn bipolar transistors Q1 through Q5 are represented by VBE1 through VBE5, respectively. The current amplification rate .beta. of each of the bipolar transistors Q1 through Q5 is sufficiently large and hence the base potentials thereof can be neglected. Let's also assume that the currents which flow through the resistors R1 through R4 are I1 through I4, respectively.
The difference between the constant voltage VCS and the second supply voltage VEE is given by the sum of the base-emitter voltage VBE5 of the bipolar transistor Q5 and the voltage drop across the resistor R4. Thus, the voltage difference VDIF' is represented by the following equation: ##EQU4##
The difference between the supply voltages VCC and VEE is given by the sum of the voltage drop across the resistor R1 and the base-emitter voltage VBE2 of the bipolar transistor Q2, and the voltage drop across the resistor R2 and the base-emitter voltage VBE1 of the bipolar transistor Q1. Accordingly, the difference therebetween is expressed by the following equation: EQU VCC-VEE=R1.multidot.I1+VBE2+R2.multidot.I2+VBE1 (b)
In addition, the difference between the supply voltages VCC and VEE is also given even by the sum of the voltage drop across the resistor R1 and the base-emitter voltage VBE4 of the bipolar transistor Q4, and the voltage drop across the resistor R4 and the base-emitter voltage VBE5 of the bipolar transistor Q5. Thus, the difference therebetween is given by the following equation: EQU VCC-VEE=R1.multidot.I1+VBE4+R4.multidot.I4+VBE5 (c)
The voltage drop across the resistor R4 is given by the following equation (d) in accordance with the above equations (b) and (c): EQU R4.multidot.I4=VBE1+VBE2+R2.multidot.I2-VBE4-VBE5 (e)
Here, the base-emitter voltage VBE5 of the bipolar transistor Q5 is given even by the sum of the base-emitter voltage VBE3 of the bipolar transistor Q3 and the voltage drop across the resistor R3. Therefore, the VBE5 is represented as follows: EQU VBE5=VBE3+R3.multidot.I3 (f)
As described above, the current which flows into each of the bases of the bipolar transistors Q1 and Q3 is sufficiently small and can be neglected as compared with the currents I2 and I3 which flow through the resistors R2 and R3, respectively. Therefore, the relationship between I2 and I3 can be expressed as follows: EQU I2.apprxeq.I3 (g)
The voltage drop across the resistor R2 is given by the following expression in accordance with the equations (f) and (g): ##EQU5## If the equation (h) is substituted in the equation (e), then the equation (e) can be rewritten as follows: EQU VDIF'=VBE1+VBE2-VBE4+(VBE5-VBE3).multidot.R2/R3 (i)
Each of the currents I1 through I4 varies according to the variations in the supply voltages VCC and VEE. However, the variations in the base-emitter voltages VBE of the bipolar transistor caused by the current variations are extremely small. It is thus understood from the above equation (i) that the VDIF' is kept constant at all times independent of the variations in the supply voltages VCC and VEE.
Accordingly, if the voltage drop over the internal VEE interconnection can be neglected, the current supplied from each of the constant current sources can always be set to a predetermined value without being affected by the variations in the supply voltages VCC and VEE.
Let's now consider the influence of the variations in the first and second supply voltages VCC and VEE in the semiconductor integrated circuit on the operation of each of the ECL logic circuits.
FIG. 6 schematically shows the layout of supply voltages VCC and VEE interconnections and signal input stage in the conventional semiconductor integrated circuit. FIG. 6 also shows an ECL.multidot.RAM as the semiconductor integrated circuit by way of example.
Referring to FIG. 6, a RAM chip 100 is provided thereon with input signal pads 9a, 9b, input buffer circuits 10a, 10b each as one of ECL logic circuits, for receiving an input signal fed from associated input signal pad 9a, and ECL logic circuits 15 each for preforming a predetermined logic operation in response to a signal from associated input buffer circuits 10a, 10b. Since the input buffer circuits 10a, 10b and the ECL logic circuits 15 are symmetrically provided on opposite sides of the RAM chip 100 in FIG. 6, the ECL logic circuits 15 positioned on opposite sides are denoted by the same reference numeral.
The ECL logic circuits 15 receive the input signals from the associated input buffer circuits 10a, 10b through interconnections 17a, 17b, respectively.
In order to supply an operating supply voltage to the input buffer circuits 10a, 10b and the ECL logic circuit 15, internal VCC interconnections 4 extending from a VCC pad 2 are formed on the RAM chip 100 along the outer periphery of the RAM chip 100, and internal VEE interconnections 12 are formed along the outer periphery of a memory cell array 1.
FIG. 7 is a diagram specifically illustrating one example of the arrangement of the input buffer circuits 10a, 10b and the ECL logic circuit 15 shown in FIG. 6.
Referring to FIG. 7, the input buffer circuit 10a is structurally identical to the input buffer circuit 10b. The input buffer circuit (ECL logic circuit) 10a includes npn bipolar transistors 107a, 108a for switching a current path according to the magnitude of a signal applied to the input signal pad 9a and the magnitude of a first reference potential VBB, resistors 205a, 206a for converting current signals fed from the bipolar transistors 107a, 108a respectively into voltage signals, and an npn bipolar transistor 109a for level-shifting a voltage signal produced by the resistor 206a.
The npn bipolar transistors 107a, 108a have emitters connected together to a constant current source 306a. The bipolar transistors 107a, 108a have collectors, respectively, connected to the internal VCC interconnection 4 through the resistors 205a, 206a. The npn bipolar transistors 107a, 108a have bases supplied with an input signal through the input signal pad 9a and a reference potential VBB1 through an internal VBB interconnection 8a, respectively. A constant current source 307a is electrically connected to the emitter of the bipolar transistor 109a.
Similarly, the input buffer circuit (ECL logic circuit) 10b includes npn bipolar transistors 107b, 108b, 109b, constant current sources 306b, 307b, and resistors 205b, 206b. The electrical connections of the input buffer circuit 10b are identical to that of the input buffer circuit 10a. They simply differ in a suffix applied to the reference numerals.
The ECL logic circuit 15 is one of peripheral circuits of the ECL.multidot.RAM. The ECL logic circuit 15 includes npn bipolar transistors 110, 111, 112 having emitters connected together, resistors 207, 208, and a constant current source 308. The npn bipolar transistors 110, 111 have collectors, connected in common to one end of the resistor 207. The bipolar transistors 110, 111 have bases supplied with output signals from the input buffer circuits 10b, 10a through the interconnections 17b, 17a, respectively. The other end of the resistor 207 is electrically connected to the internal VCC interconnection 4. The bipolar transistor 112 has a collector connected to the internal VCC interconnection 4 through the resistor 208, and a base supplied with a third reference potential VBB2 through an interconnection 8c. An output signal of the ECL logic circuit 15 is produced at the collector of the bipolar transistor 112.
The constant current sources 306a, 307a, 306b, 307b, 308b are supplied with currents through the internal VEE interconnection 12, and supply the currents to their corresponding transistors. A description will now be made of the operations of the input buffer circuits 10a, 10b.
Since the operations of the input buffer circuits 10a, 10b are identical to each other, the operation of the input buffer circuit 10a will be described below. The operation of each of the input buffer circuits 10a, 10b is the same as that of the input buffer circuit 10 shown in FIG. 3. In this case, an input signal applied to each of the input buffer circuits 10a, 10b is not subjected to the level shifting, and as an alternative it is level-shifted at the output.
When a signal VIH of a high level is inputted to the input signal pad 9a, the bipolar transistor 107a is brought into an "ON" state and the bipolar transistor 108a is brought into an "OFF" state if the signal VIH of the high level is higher in level than the reference potential VBB1. As a consequence, the potential at the collector of the bipolar transistor 108a is rendered high. The collector potential of this bipolar transistor 108a is level-shifted by the base-emitter voltage VBE of the bipolar transistor 109a and then supplied to the interconnection 17a. The voltage V17H of a signal of a high level, which is supplied to the internal output interconnection 17a, is represented by the following equation: EQU V17H=VBE-.DELTA.V4
On the other hand, when a signal VIL of the low level lower than the reference potential VBB1 is applied to the input signal pad 9a, the bipolar transistor 107a is brought into the "OFF" state and the bipolar transistor 108a is brought into the "ON" state. As a consequence, the potential at the collector of the bipolar transistor 108a is rendered low in level and the potential at the emitter of the bipolar transistor 109a, i.e., the output voltage at the internal output interconnection 17a of the ECL logic circuit (input buffer circuit) 10a is also rendered low in level. Assuming now that the resistance value of the resistor 206 is R206, and the current which flows through the constant current source 306a is I306, the potential V17L of a signal of a low level at the internal output interconnection 17a is given by the following equation: EQU V17L=-R206.multidot.I306-VBE-.DELTA.V4
If VBB1 meets the relation of VIL&lt;VBB1&lt;VIH, the input buffer circuits 10a, 10b are normally operated. The switching speed of each of the input buffer circuits 10a, 10b becomes faster as the amplitude V17H-V17L=R206.multidot.I306 is decreased. The switching speed also becomes slow as the reference potential VBB1 is shifted from the center between the low-level voltage VIL and the high-level voltage VIH.
A description will now be made of the operation of the ECL logic circuit 15. When either one of the outputs 17a and 17b (the internal signal interconnection and signal supplied to the internal signal interconnection are denoted by like reference numerals) of the input buffer circuits 10a, 10b, respectively, is high in level, either one of the bipolar transistors 110, 111 is brought into the "ON" state and the bipolar transistor 112 is brought into the "OFF" state if the high-level potential V17H is higher than the reference potential VBB2. As a consequence, the potential at the collector of the bipolar transistor 112 is rendered high.
When both outputs 17a, 17b of the input buffer circuits 10a, 10b are low in level, the two bipolar transistors 110, 111 are brought into the "OFF" state and the bipolar transistor 112 is brought into the "ON" state if the low-level potential V17L is lower than the reference potential VBB2. As a consequence, the potential at the collector of the bipolar transistor 112 is rendered low.
If the reference voltage VBB2 lies between V17L and V17H (i.e., V17L&lt;VBB2&lt;V17H), the ECL logic circuit 15 is normally operated at all times. The switching speed of the ECL logic circuit 15 becomes faster as the amplitude of output therefrom is decreased as in the case of the input buffer circuits 10a, 10b. The switching speed thereof becomes slower as the reference potential VBB2 is shifted from the center between the low-level voltage V17L and the high-level voltage V17H.
Let's now assume that the current supplied from the constant-current source is kept constant without being affected by the variation in the second supply voltage VEE. As shown in the above equation (8), the reference potential V (8) of the input buffer circuit 10 undergoes a great influence of the voltage drops at the interconnection 8 and the internal VCC interconnection 4. The variation in the reference potential V (8) exerts a great influence on the operation margin and speed of the semiconductor integrated circuit which deals with a signal of the ECL level.
In order to control the variation in the reference potential V (8) of each input buffer circuit, which variation is caused by the supply voltage, process parameters, temperature, or the like, it is necessary to reduce the voltage drops .DELTA.V4, .DELTA.V8 caused by the interconnection resistances as small as possible. The resistor R201, the base-emitter voltage VBE and the like also undergo the influence of the process parameters and temperature. However, it is possible to minimize the variation in the reference potential V (8) to be within the minimum allowable range in design specifications. However, since the interconnections 4, 8 extend over the semiconductor chip and the supply voltages are directly supplied thereto, the reference potential undergoes the greatest influence of these factors.
In addition, since the distances from different input buffer circuits to the VCC pad and the VBB1 generating circuit are different from one another, the voltage drops .DELTA.V4, .DELTA.V8 caused by the interconnection resistances at the interconnections 4, 8 differ for each input buffer circuit. It is therefore necessary to minimize the voltage drops .DELTA.V4, .DELTA.V8 caused by the interconnection resistances even from the above standpoint.
In order to minimize the voltage drop .DELTA.V4 at the internal VCC interconnection 4 to a negligible level, the reference potential generating circuit 11 is normally provided near the VCC pad 2 as shown in FIG. 1.
The length of the interconnection 8 becomes longer with an increase in the scale of the semiconductor integrated circuit. However, since the width of the interconnection 8 cannot be made larger in view of the area of the layout of the semiconductor integrated circuit, the resistance of the interconnection 8 becomes large. The current which flows through the interconnection 8 corresponds to that which flows into the base of each bipolar transistor. However, inasmuch as the number of the input buffer circuits connected to the interconnection 8 are increased in a large-scale semiconductor integrated circuit, the total amount of currents which flow into the bases of the bipolar transistors cannot be neglected. For 64K.times.4 bit type ECL.multidot.RAM, twenty-two input buffer circuits are required. Assuming now that the resistance value of the interconnection 8 is 100 .OMEGA., the base current which flows from one input buffer circuit 10 to the interconnection 8 is 0.05 mA, the voltage drop .sub..DELTA. V8 at the interconnection 8 reaches the maximum 0.11 V from the calculation of 0.05.multidot.10.sup.-3 .multidot.100.multidot.22. As a consequence, this voltage drop exhibits a large value with respect to 0.8 V representing the amplitude (VIH-VIL) of a signal inputted in the ECL logic circuit. Thus, the voltage drop .DELTA.V8 at the interconnection 8 becomes a greater value in the conventional semiconductor circuit, and hence the variation in the reference potential V (8) which occurs in an integrated circuit or between integrated circuits cannot be neglected, said variation being caused by the supply voltages or the process parameters, or the like. If the reference potential V (8) varies in this way, the operating margin of each input buffer circuit is reduced and the operating speed of each input buffer circuit is slow, thus causing an increase in the delay at the input buffer circuit.
The influence of the voltage drop at the internal VEE interconnection 12 on the current supplied from the constant current source has been neglected in the above discussion. However, such a voltage drop cannot be neglected.
When the constant current sources shown in FIGS. 4A through 4C are used, the values of the currents therefrom are different from each other due to the voltage drop .DELTA.V12 over the internal VEE interconnection 12. When the constant current source shown in FIG. 4A, for example, is used as the constant current source in the ECL logic circuit shown in FIG. 7, the low-level potential V27L of each of the outputs 17a and 17b from the ECL logic circuits (input buffer circuits) 10a, 10b is given by the following equation: EQU V17L=-a.multidot.R206.multidot.(VDIF-.DELTA.V12-V.sub.BE)-VBE-.DELTA.V4
The high-level potential V17H is also given by the following equation: EQU V17H=VBE-.DELTA.V4
It is to be understood that the output levels of the ECL logic circuits 10a, 10b vary according to the voltage drops .DELTA.V4 and .DELTA.V12 at the power supply interconnections, respectively.
In addition, as seen from FIGS. 1 and 6, the internal power supply interconnections 4, 12, which extend from the power supply pads 2, 3, respectively, are different in length from each other with respect to the input buffer circuit 10a, 10b. Therefore, their resistance values are different from each other, and the outputs 17a, 17b generated from the input buffer circuits 10a, 10b, respectively, are different in the voltage drops .DELTA.V4, .DELTA.V12 from each other. Accordingly, the voltage level of the output 17a and the voltage level of the output 17b differ from each other even if they exhibit the same logic value.
When the amplitude of each of the outputs 17a, 17b is decreased to make faster the switching speed of the ECL logic circuit, the range of the reference potential VBB2, i.e., V17L&lt;VBB2&lt;V17H, which is required for operating the ECL logic circuit 15 normally, is made narrower. When the outputs 17a and 17b differ in level from each other in particular, the lower limit of the range of the reference potential VBB2, which is necessary for normally operating the ECL logic circuit 15, is determined by higher one of the low level potentials of the outputs 17a, 17b. On the other hand, the upper limit of the range of the reference potential VBB2 is determined by lower one of the high level potentials of the outputs 17a, 17b. Therefore, the range of the reference potential VBB2, which is required for normally operating the ECL logic circuit 15, is made narrower.
Since the reference potential VBB2 is easily shifted from the center between the high-level potential V17H and the low-level potential V17L owing to some variations in the reference potential VBB2, the operating speed of the ECL logic circuit 15 also become slow. Let's now assume that, for example, the resistance 4c, 12a of the power supply interconnections between the input buffer circuits 10a and 10b are 10 .OMEGA. respectively, a preset value a.multidot.(VDIF-V.sub.BE) of the constant current from the constant current source 306 is 1 mA, the difference (VDIF-V.sub.BE) is 1 V, the resistance value R206 of the resistor 206 is 0.5 K.OMEGA., the power supply current which flows through the internal VCC interconnection 4 is 10 mA, and the power supply current which flows through the internal VEE interconnection 12 is 10 mA. Then, if the above power supply currents flow from the input buffer circuit 10a to the input buffer circuit 10b, the difference between the high-level potential of the output 17a and the high-level potential of the output 17b becomes 0.1 V and the difference between the low-level potential of the output 17a and the low-level potential of the output 17b becomes 0.05 V. In this case, the preset value of the amplitude of each of the outputs 17a and 17b is 0.5 V. However, the range of the reference potential VBB2, which is necessary to normally operate the ECL logic circuit 15, falls within 0.35 V due to the resistance of each internal power supply interconnection.
Accordingly, the conventional semiconductor integrated circuit has the problem that the output level of the ECL logic circuit varies under the influence of the voltage drop caused by the resistance of each power supply interconnection, and the reduction in the amplitude of each output for performing an operation in the ECL logic circuit at high speed cannot be carried out, which reduction is required for acquiring sufficient operating margin and the switching speed of subsequent logic circuitry. This problem is developed more prominently due to the increasing capacity of the semiconductor integrated circuit accompanied with increases in the interconnection length and the current which flows through the interconnection.
The influence of the voltage drops at the above-described power supply interconnections occurs even in the case where the semiconductor integrated circuit includes TTL logic circuitry or MOS logic circuitry as well as where it includes ECL logic circuitry. In addition, their influence also appears not only in the input buffer circuits but also in other arbitrary internal logic circuitry.
The architecture for eliminating the adverse impact of a voltage drop at the power supply interconnection on the reference potential of the ECL logic circuit is disclosed in the article "BiCMOS Current Source Reference Network for ULSI BiCMOS with ECL circuitry", by H. V. Tran et. al. in 1989 IEEE ISSCC Digest of Technical Papers, Feb. 1989, p.p. 120-121. The architecture of the prior art includes a global level reference generator for producing a reference current flowing through a long interconnection line over a chip, and a local level reference generator provided near an associated ECL circuit or an associated constant current source to receive the reference current to thereby produce the reference potential level for application thereof to the associated ECL circuit or current source.